FIG. 1 illustrates an imaging device 100 having a CMOS pixel array 140. Row lines of the array 140 are selectively activated by a row driver 145 in response to row address decoder 155. A column driver 160 and column address decoder 170 are also included in the imaging device 100. The imaging device 100 is operated by the timing and control circuit 150, which controls the address decoders 155, 170. The control circuit 150 also controls the row and column driver circuitry 145, 160.
The following devices form the readout chain of the imaging sensor 100. A sample and hold circuit 161 associated with the column driver 160 samples and holds a pixel reset signal Vrst and a pixel image signal Vsig for each selected pixel of the array 140. A differential signal (Vrst−Vsig) is produced by a differential amplifier 162 for each pixel and is digitized by analog-to-digital converter 175 (ADC). The analog-to-digital converter 175 supplies the digitized pixel signals to an image processor 180, which forms and may output a digital image.
The output of an imaging device 100 is very sensitive to operational amplifier (“opamp”) offset voltage. The offset voltage is the voltage required across the input terminals of the operational amplifier to drive the output voltage to zero. In an ideal operation amplifier, there would be no offset voltage required. However, offset voltage is required in real-world operational amplifiers because of internal imperfections. Some industry techniques have been developed to reduce the offset voltage together with noise (which has similar characteristics as offset voltage at low frequencies). These techniques, described below, include chopper stabilization, auto-zero, and correlated double sampling (CDS). In the chopper stabilization technique, the input signal is modulated with a high frequency carrier before amplification and is then demodulated after amplification to obtain an amplified version of the input signal. The offset voltage is modulated only once in the path and is filtered out with a subsequent low-pass filter. The main drawbacks of chopper stabilization are that it is bandwidth limited to half of the chopper frequency to avoid signal aliasing, and that it requires filtering to remove the large ripple voltages generated by chopping.
FIG. 2 is a schematic diagram of a conventional auto-zero amplifier 200. Amplifier 200 includes a primary amplifier AB, an auxiliary amplifier AA, two auto-zero phase switches 201, 202, controlled by an auto-zero phase signal ΦA, for use during an auto-zero phase, and two amplification phase switches 203, 204, controlled by an amplification phase signal ΦB, for use during an amplification phase. Amplifier 200 further includes biasing capacitors VOSA, CM1, CM2. The primary amplifier AB includes a non-inverting input 210, an inverting input 220, an offset nulling port BB, and an output 250. The auxiliary amplifier AA includes a non-inverting input 230, an inverting input 240, an offset nulling port −BA, and an output 260.
As shown in FIG. 2, during the auto-zero phase, the auxiliary amplifier AA is configured in unity gain feedback (i.e., the output tracks the input without amplification) between the output port 260 and the offset nulling port −BA, while inputs of the auxiliary amplifier AA are shorted by closing the auto-zero phase switches 201, 202 and opening the amplification phase switches 203, 204. The biasing condition of the nulling port −BA is sampled in the auto-zero phase and held throughout the subsequent amplification phase, when the amplification phase switches 203, 204 are closed and the auto-zero phase switches 201, 202 are open. This results in an almost offset voltage-free auxiliary amplifier AA in the amplification phase.
In the amplification phase, the signal path VOA has significantly more gain (primary amplifier AB gain times auxiliary amplifier AA gain) than the offset path VNA (primary amplifier AB gain). Thus, the equivalent input offset voltage of the amplifier 200 is greatly reduced by the gain ratio of the two paths VOA, VNA. Drawbacks of this conventional design are that it requires two amplifiers AA, AB and it often has a larger layout area than other amplifier designs.
FIG. 3 is a schematic diagram of a conventional amplifier 300 with offset compensation for auto-zeroing. Amplifier 300 includes a distributed amplifier 310, an offset compensation block 320, and a two-stage amplifier 330. The distributed amplifier includes first and second transistors m1, m2, first and second resistance circuits R1, R2, a first biasing transistor Bias, an input terminal IN, a reference voltage input REF, and a switch 311 controlled by an auto-zero signal AZ for connecting the input terminal IN to the reference voltage input REF. The offset compensation block 320 includes third and fourth transistors m3, m4, a second biasing transistor B, two capacitors C1, C2, and two switches 321, 322 controlled by the auto-zero signal AZ. Two-stage amplifier 330 includes first and second amplifiers A1, A2, where the second amplifier A2 outputs to two switches 331, 332, each controlled by an inverse auto-zero signal/AZ. The first amplifier A1 inputs signals from the distributed amplifier 310 via a pair of capacitors 327, 328, each connected to a respective switch 325, 326, respectively connected to the first and second transistors m1, m2. Switches 331, 332 receive signals from the offset compensation block 320 via switches 321, 322.
This configuration implements offset cancellation using the same principle as the auto-zero phase of the auxiliary amplifier AA presented in FIG. 2. A drawback of this design is that the phase margin of the signal path will be jeopardized due to the additional offset compensation block 320 before the traditional two-stage amplifier 330. In addition, more noise may be introduced due to additional CMOS elements in the offset compensation block.
Correlated double sampling (CDS) is another approach to reduce the offset voltage and noise. Correlated double sampling typically involves two steps of sampling. The first step samples the offset voltage and stores the sampled offset voltage in a capacitor. The second step samples both the offset voltage and the signal and performs a difference operation with the offset voltage sampled in the first step. The offset voltage is thus ideally cancelled out by correlated double sampling.
FIG. 4 is a schematic diagram of a conventional circuit 400 for implementing correlated double sampling. Circuit 400 includes an ideal operational amplifier 410, having two inputs 411, 412 and an output 413. An offset voltage source Vos is connected in series with input 411. Circuit 400 further includes three switches 415, 420, 425. Switches 420, 425 are controlled by a first phase signal phi1, and switch 415 is controlled by a second phase signal phi2.
In a first phase, the first phase signal phi1 is asserted, closing switches 420 and 425, and the operational amplifier 410 is configured in unity gain feedback, such that the output tracks the input without amplification. An offset voltage is sampled and stored in an offset capacitor Cos. In a second phase, the second phase signal phi2 is asserted, closing switch 415, and the voltage stored in offset capacitor Cos is used to cancel the offset voltage of the operational amplifier 410. This implementation has a disadvantage in that the operational amplifier 410 is required to be unity-gain stable, which is usually difficult and unnecessary in certain cases. In addition, due to the input parasitic capacitance of the operational amplifier, the feedback factor is usually degraded undesirably.
FIG. 5 is a circuit diagram of a conventional differential telescopic operational amplifier 500. Amplifier 500 includes first through tenth transistors 505, 510, 515, 520, 525, 530, 535, 540, 545, 550. First through fourth transistors 505, 510, 515, 520 are p-type transistors. Fifth through tenth transistors 525, 530, 535, 540, 545, 550 are n-type transistors. Transistors 505, 515, 525, 535, 545 are connected in series, and transistors 510, 520, 530, 540, 550 are connected in series.
Transistors 505, 510 have their gates connected to each other and to a first line 555, which is connected to a first bias output BIASP. Transistors 515, 520 have their gates connected to each other and to a second line 560, which is connected to biasing circuitry (not shown). Transistors 525, 530 have their gates connected to each other and to a third line 565, which is connected to biasing circuitry (not shown). A first signal output OUTN is located between transistors 515, 525. A second signal output OUTP is located between transistors 520, 530. Transistors 535, 540 receive first and second signal inputs INP, INN at their respective gates. A third line 570 is connected between transistors 535, 545, and between transistors 540, 550, and is connected to biasing circuitry (not shown). A fourth line 575 is connected to biasing circuitry (not shown), and to a gate of the ninth transistor 545, and to a second bias output BIASN. A common mode feedback input CMFB is connected to a gate of the tenth transistor 550 for receiving a common mode feedback based on the outputs OUTP, OUTN. Amplifier 500 has a disadvantage in that the biases of the first and second transistors 505, 510 are fixed and reliant on each other.
Accordingly, there is a need and desire for a method and apparatus for providing offset compensation for an operational amplifier to minimize the offset voltage in a readout chain of an imaging device.